plans for this thing:
- orthogonal instruction set
- 16 bit instruction word: 6 bit opcode, 10 bit address/data
- two 8k×8 eeproms used for main memory (maybe use sram or fram instead)
- low 1k words used for program memory, remainder is available as wram and data by paging instructions
- 16 bit ALU, functions tbd
re: plans for this thing:
@Felthry budget for it, and it's yours.
re: plans for this thing:
@eryn yeah but that will be easier when we're not unsure whether we're even going to have a job after august
re: plans for this thing:
might need to use a harvard architecture if I want pipelining though