everyone around us does programming, there are so few people we can talk hardware with
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@Felthry
I'm working on a lab assignment to implement VGA on an FPGA trainer board!
@Tathar Ooh, fun, I remember doing that! How's it going?
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I have a multi-driven pin somehow, and Vivado's lying about where the error is.
I'm not entirely sure how to read this message though:
[Synth 8-6859] multi-driven net on pin vga/hs[0] with 1st driver pin 'Hsync_OBUF_inst_i_2/O' ["C:/Users/Tathar/Xilinx/EEL5722C/Lab2/Lab2.srcs/sources_1/new/Lab2.v":18]
I'm guessing this is the module instance "vga" with bit 0 on port name "hs" being driven by something to do with "Hsync" but the only case-sensitive example of that last one is an output on my top-level module and it isn't driving anything else. The code line it's pointing to is in my parameterized clock enable module, and there shouldn't be anything wrong with that because I've used it before in a different design.
The other message is:
[Synth 8-6859] multi-driven net on pin vga/hs[0] with 2nd driver pin 'Hsync_OBUF_inst_i_3/O' ["C:/Users/Tathar/Xilinx/EEL5722C/Lab2/Lab2.srcs/sources_1/new/Lab2.v":18]
Which still doesn't make sense to me.
@Tathar Okay, since we don't know verilog and remember little of vhdl (it was like six years ago and we haven't used it since), i'll just explain like this
say you have some sort of code that says "for each input x1 through x5, do this to it and output the result to outputs y1 through y5", so each yn is a function of xn only
if you messed up and said "for each input x1 through x5, do this to it and output the result to output y1", then you'd have y1 simultaneously driven by five circuits
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Still trying to find the culprit, but I think I narrowed it down.
I think I just found the problem, but the error messages point to something else entirely.
@Tathar welcome to programming!
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The TA said I should use one file per module instead of putting everything in one file. Does that help anything?
@Tathar Sorry, we don't know anything about verilog.
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Would that be the case for VHDL?
@Tathar Probably not? Splitting stuff into files is usually more for organization than anything, it wouldn't cause an error unless you forgot an include statement somewhere
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That's what I thought too.
As far as I know, Verilog and VHDL should be functionally identical, just with a different syntax.
@Tathar That's true of any two programming languages too, though. Or any two natural languages!
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I mean in the sense of there not being anything without a perfect translation, which can happen at least for natural languages.
@Felthry
It's Verilog, yeah. I would be allowed to use VHDL for the lab, but I don't know it at all.
Can you elaborate on the instancing part? I'm not entirely sure what I should be looking for.