everyone around us does programming, there are so few people we can talk hardware with
-F
@Felthry
I'm working on a lab assignment to implement VGA on an FPGA trainer board!
@Tathar Ooh, fun, I remember doing that! How's it going?
-F
I have a multi-driven pin somehow, and Vivado's lying about where the error is.
I'm not entirely sure how to read this message though:
[Synth 8-6859] multi-driven net on pin vga/hs[0] with 1st driver pin 'Hsync_OBUF_inst_i_2/O' ["C:/Users/Tathar/Xilinx/EEL5722C/Lab2/Lab2.srcs/sources_1/new/Lab2.v":18]
I'm guessing this is the module instance "vga" with bit 0 on port name "hs" being driven by something to do with "Hsync" but the only case-sensitive example of that last one is an output on my top-level module and it isn't driving anything else. The code line it's pointing to is in my parameterized clock enable module, and there shouldn't be anything wrong with that because I've used it before in a different design.
So it turns out that my clock divider module [around the specified line of code] did in fact have a bug: the divisor had an off-by-one error, and occasionally it was possible for multiple non-blocking assignments to drive the counter register. This ended up changing its effect from dividing the 100 MHz clock down to a 25 MHz pixel clock, to instead divide it to 40 MHz.
@Felthry
It works now.
https://youtu.be/V60_zIKBviI