okay so the PIC has fifteen level triggered interrupt lines and one edge triggered nonmaskable line

you can disable the level triggered ones by turning off the interrupt flag (cli turns it off, sti turns it on, it's also turned off upon ISR transfer) but the edge triggered line will always cause interrupts

you can also trigger sixteen different software interrupts with an instruction, for syscalls or whatever

which means the vector table will have 32 addresses

i might add more

to clarify, i might add more for interrupts that the processor itself can trigger if the code does something bad, like try to access a nonexistent memory address

so the faults the processor can trigger are:
- invalid memory read/write (tried to read/write an address that doesn't exist)
- invalid pointer address (tried to read instruction from an address that doesn't exist)
- invalid instruction

trying to think of if it's worth it to try implementing rings...

am i seriously contemplating implementing protection rings on my weird retro fantasy processor

what is wrong with me. it's like i'm hastily and terribly recapitulating the history of processor design

i have decided not to implement protection rings

SO, what this means is that the processor can generate three different faults
with that in mind, here's the breakdown of interrupt causes:
- 16 from an instruction
- 3 faults
- 1 NMI level-triggered line
- 12 external maskable interrupts