processor stuff
okay so the PIC has fifteen level triggered interrupt lines and one edge triggered nonmaskable line
you can disable the level triggered ones by turning off the interrupt flag (cli turns it off, sti turns it on, it's also turned off upon ISR transfer) but the edge triggered line will always cause interrupts
you can also trigger sixteen different software interrupts with an instruction, for syscalls or whatever
which means the vector table will have 32 addresses
i might add more
processor stuff
so the faults the processor can trigger are:
- invalid memory read/write (tried to read/write an address that doesn't exist)
- invalid pointer address (tried to read instruction from an address that doesn't exist)
- invalid instruction
trying to think of if it's worth it to try implementing rings...
processor stuff
@typhlosion This is so cool, I didn't know it was possible to just, design things like this
processor stuff
@VoxSomniator people don't do it very much because everyone just uses x86 or ARM processors
processor stuff
@VoxSomniator @typhlosion FPGAs or ASICs with custom HDL are used in all sorts of things where it turns out to be cheaper than getting a super-advanced x86 or ARM processor. You can do very specific timing, too, so they're absolutely essential in oscilloscopes for example to interlace like a dozen different high-speed ADCs