re: plans for this thing:
might need to use a harvard architecture if I want pipelining though
plans for this thing:
- orthogonal instruction set
- 16 bit instruction word: 6 bit opcode, 10 bit address/data
- two 8k×8 eeproms used for main memory (maybe use sram or fram instead)
- low 1k words used for program memory, remainder is available as wram and data by paging instructions
- 16 bit ALU, functions tbd
- insist on including workarounds for hardware bugs that exist in very specific, obsolete, and possibly nonexistent processors
Plural system of three, Felthry, Alaric and Rosemary. We'll sign posts with a -F, -A, or -R.
Autistic, 20-something, anxious mess
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#FelthrysVGMSelection for my music picks.
Current avatar by @hi_cial