processor stuff 

okay so the PIC has fifteen level triggered interrupt lines and one edge triggered nonmaskable line

you can disable the level triggered ones by turning off the interrupt flag (cli turns it off, sti turns it on, it's also turned off upon ISR transfer) but the edge triggered line will always cause interrupts

you can also trigger sixteen different software interrupts with an instruction, for syscalls or whatever

which means the vector table will have 32 addresses

i might add more

processor stuff 

@typhlosion Which PIC are you emulating?

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processor stuff 

@Felthry as with everything else in this project, my own thing

i guess it's dishonest to say it's a proper PIC, it's just kind of a separate piece that i'm adding to handle interrupts for the sake of modularity

processor stuff 

@typhlosion oh! Okay. I need to try to follow this better.

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