processor stuff
okay so the PIC has fifteen level triggered interrupt lines and one edge triggered nonmaskable line
you can disable the level triggered ones by turning off the interrupt flag (cli turns it off, sti turns it on, it's also turned off upon ISR transfer) but the edge triggered line will always cause interrupts
you can also trigger sixteen different software interrupts with an instruction, for syscalls or whatever
which means the vector table will have 32 addresses
i might add more
processor stuff
@typhlosion Which PIC are you emulating?
processor stuff
@typhlosion oh! Okay. I need to try to follow this better.