processor stuff
okay so the PIC has fifteen level triggered interrupt lines and one edge triggered nonmaskable line
you can disable the level triggered ones by turning off the interrupt flag (cli turns it off, sti turns it on, it's also turned off upon ISR transfer) but the edge triggered line will always cause interrupts
you can also trigger sixteen different software interrupts with an instruction, for syscalls or whatever
which means the vector table will have 32 addresses
i might add more
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so the faults the processor can trigger are:
- invalid memory read/write (tried to read/write an address that doesn't exist)
- invalid pointer address (tried to read instruction from an address that doesn't exist)
- invalid instruction
trying to think of if it's worth it to try implementing rings...
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am i seriously contemplating implementing protection rings on my weird retro fantasy processor
what is wrong with me. it's like i'm hastily and terribly recapitulating the history of processor design
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i have decided not to implement protection rings
SO, what this means is that the processor can generate three different faults
with that in mind, here's the breakdown of interrupt causes:
- 16 from an instruction
- 3 faults
- 1 NMI level-triggered line
- 12 external maskable interrupts
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the fact that there are 12 interrupts means i could theoretically mask them individually using a single register. i dunno if there's room for it tho
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💻 IT'S ✨ HAPPENING 💻
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@typhlosion Which PIC are you emulating?
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@Felthry as with everything else in this project, my own thing
i guess it's dishonest to say it's a proper PIC, it's just kind of a separate piece that i'm adding to handle interrupts for the sake of modularity
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@typhlosion oh! Okay. I need to try to follow this better.
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@typhlosion This is so cool, I didn't know it was possible to just, design things like this
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@VoxSomniator people don't do it very much because everyone just uses x86 or ARM processors
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@typhlosion @VoxSomniator Look up 'soft cores'. They're CPUs written in VHDL or Verilog designed to be put onto an FPGA or CPLD and expanded upon!
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@VoxSomniator @typhlosion FPGAs or ASICs with custom HDL are used in all sorts of things where it turns out to be cheaper than getting a super-advanced x86 or ARM processor. You can do very specific timing, too, so they're absolutely essential in oscilloscopes for example to interlace like a dozen different high-speed ADCs
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@Felthry @typhlosion Oh my god, I've looked into FPGA stuff before and it's so cool. I can't comprehend any of it, but still, cool stuff
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to clarify, i might add more for interrupts that the processor itself can trigger if the code does something bad, like try to access a nonexistent memory address